Electrical Engineering Services

Purpose built for a wireless power transfer application that uses inductively coupled, galvanically isolated technology. The design includes two Thermal Clad Insulated Metal Substrate (TCLAD) PCBs for thermal conduction, physical isolation between primary and secondary components, and various electrical, mechanical, thermal, and PCB designs. The application controls battery voltage in a metric ton battery and includes features such as plexiglass partition wall, perimeter seal, ground stud, ethernet connectors, and faceplate heatsink. The design also includes mill-max pogo spring pins and pads, 23-pin round ethernet connectors, and a die-cut conductive thermal gap pad. The assembly uses flywire pin leads to Phoenix connectors.

Design Features/Constraints

• Mill-Max Pogo Spring Pins and Pads for communicating from T-Clad to PCB
• 23 Pin Round Ethernet Connectors w/EMI Gasket Conn Pins Feed to Ethernet Mill-Max Pin Holders
• Faceplate & T-Clad is Pinned Diagonally to help Set Orientation
• 2x 5 Pin round Ethernet Connectors w/EMI Gaskets
• Conn Pins Feed to Ethernet Mill-Max Pin Holders
• Die Cut Conductive Thermal Gap Pad 3 W/m-K
• Exterior Faceplate Heatsink
• Wireless Power Transfer Assembly
• w/Flywire Pin Leads to Phoenix Conn

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The primary purpose of 72 Port Switch Card is to reduce cable count and complexity in highly integrated Infiniband switch systems. This approach was initially utilized to create a switching matrix as the heart of a supercomputer. The 72 Port Switch Card is a subset of the full design and was meant to support localized nodes with a moderate concentration of local I/O requirements. This might serve as a separate building or a separate group within the overall network. The Primary protocol is Infiniband with other protocol and interface translation accomplished externally as needed. Most communications are expected to utilize Infiniband in order to maximize speed and throughput of the overall system. It works by routing external data to a fabric card that is able to accomplish N by N switching between any channels in the chassis. In quad data rate (QDR) mode, 10gb/s transmission rates per channel are typical. The switch element ASIC is the InfiniScaleIV (I4) from Mellanox. This device provides 36 4x QDR ports. To obtain 72 ports of IB data, six chips were employed per assembly.

The main challenge in dealing with a design of this magnitude is the routing of high speed signals. To accommodate this challenge, routing groups had to be placed on different PCB layers separated by internal ground planes. This method would guarantee the reduction of crosstalk between signal groups. Signal groups consist of signal pairs coming to and from (Tx, Rx) the outside world (IPASS connectors), and signals coming to and from (Tx, Rx) the Fabric Card. Each layer has its own unique routing format to keep signal pairs from overlapping. Utilizing a Port Allocation Table facilitated a signal naming convention that enabled a more “route friendly” method for layout.

This project was a RoHS compliant design that fit within a four physical lane PCI Express (PCIe) form factor as defined in the PCIe 2.0 specification. The height of the card was allowed to extend past the specification limits to accommodate the placement and routing of the four DDR2 memory DIMM sockets. This design was not required to support Hot Swap, WAKE, and SMB functions. The Xilinx reference designs, ML555 and ML561, were used as starting points for the electrical design of this board. The PCIe circuitry was implemented according to the ML555 reference design and the DDR2 and QDR II SRAM memory interfaces were implemented from the ML561 reference design.

The Xilinx Virtex 5 FPGA device, part number XC5VLX85T-1FF1136C, was at the core of this design. Firmware and signal pin assignments for the FPGA were provided by the customer. A pair of external 200 MHz clock sources was required by the FPGA to internally generate the DDR and QDR memory clocks. At power on, the FPGA firmware was downloaded from the configuration SPI flash device. Following configuration the device allowed and controlled PCIe accesses to the on board DDR2 and QDR SRAM memory devices.

Memory consisted of four 22.5° DIMM sockets that support 2GB, 4GB, and 8GB DDR2 memory modules for a maximum total of 32GB of DDR2 memory. The memory modules support ECC and parity, and speeds from 266 MHz to 566 MHz. A single Samsung 8 MB QDR II SRAM device was also on board supporting 300 MHz clock speeds.

A manual reset switch was implemented to reset the FPGA as required during test. Further LED status indicators were provided for the following functions:

• Green/Red for each power source, green indicates power within limits, red indicates power out of limit
• Yellow for FPGA Load DONE complete
• Blue PCI link up
• 5 Green user defined indicators connected to the FPGA

Power supply voltages and currents were implemented for the following:

• DDR2 VREF 0.9V @ 6A
• VCCINT 1.0V @ 6A
• AVTTTX/RX 1.2V @ 4A
• AVCCPLL 1.2V @ 4A
• AVCC 1.0V @ 4A
• DDR2 1.8V @6A
• VCCO 2.5V @5A
• VCCAUX 2.5V @ 5A
• PCIVCC 3.3V @5A

The required voltages were created from the 3.3V and 12V power supplied over the PCIe bus. All voltages were monitored by a Lattice in-system programmable power supply monitoring, sequencing and margining controller. Freedom CAD engineers supplied the firmware for this device which also provided power on reset to the card.